The technical field of the invention is printer controllers.
Printer controllers for computer systems have steadily grown in sophistication and performance. Digital signal processors are increasingly used to perform the wide variety of tasks required which include a high level of signal processing capability and multi-faceted interface requirements. Memory control is centralized in a memory interface controller function. These systems use increasingly large memory functions of several types, such as synchronous DRAM (SDRAM) and flash memory.
FIG. 1 illustrates the prior art steps required to process the input data that a printer typically receives from a conventional personal computer (PC). The output from the PC normally is supplied by a printer driver 101 that prepares an output print file. This file includes a set of instructions and data in a page description language (PDL) or compressed bitmap format. These instructions and data may be transported to the printer via IEEE 1284 (Firewire) or Universal Serial Bus (USB) cabling or over a local area network and stored in an input buffer memory 102.
The first computational step in the printer controller pipeline is interpretation 103 of the data. The display list from interpretation 103 includes a description of individual elements of graphics data or text data along with the position of these elements on the page. The display list may be in a banded or a non-banded format. In a banded format discrete bands are defined and formed as a part of the processing. After rendering, a number of these bands collectively form a full printer controller output page. In a non-banded format, each page is interpreted as a unit. After rendering, this unit forms an integral part of printer controller output.
The rendering pipeline stage 104 reduces the interpreted data of the display list to printer specific raster data. This process is sometimes called rasterization. The output of the rendering process is a bit map format in which discrete digitized dots (pixels) are generated to control the output device (e.g. ink jet pen, laser drum) with proportions of the colors cyan, yellow, magenta, and black. The rendering step is well suited to digital processing operations commonly used in digital signal processor devices. After rendering, the bit map data is stored in an output buffer memory stage 105. This bit map data is sent as needed to the printer output mechanism 106.
FIG. 2 illustrates a high-level view of the full complement of printer pipeline functions of the prior art. The input data has a variety of sources, such as spooled jobs on disc 201, parallel printer port 202, Universal Serial Bus (USB) port 203, Ethernet TCP/IP port 204 and IEEE 1284 (Firewire) 205. Each data source has its specific data format. This data must be reduced to a common format for processing in the pipeline. Streams interface unit 207 adjusts the format of the input data as required. For example, data arrives in parallel form from parallel printer port 202 and is converted in streams interface unit 207 as necessary for uniform processing in later stages. Likewise, streams interface unit 207 often carries out format adjustments upon data from USB port 203 in queue coming from the host processor.
Streams interface unit 207 sends data to the path that performs parallel interpretation of the composite postscript 208, printer control language PCL 210 or other PDL interpreter 210. Page pipeline block 209 re-assembles the results of the interpretation process into page format for page oriented processing before submitting page data to rendering unit 212. Postscript interpreter 208 or PCL interpreter 210 may send banded format data directly to rendering unit 212. Rendering unit 212 also performs compression, decompression or screening as required. PDL print controller to print engine controller interface unit 225 supplies data and control information to ASIC special purpose processor 213 to drive paper path control 216, the control panel/display 214 and the video data output 215.
FIG. 3 illustrates a conventional printer controller system. The system has typically a main processor 300 and a system ASIC printer controller 301, both served by a single processor bus 302. All major compute functions are carried out within the main processor 300.
The system interfacing to a personal computer (PC) 303 is directed by the system ASIC printer controller 301 via a USB port 304 or alternately by an IEEE 1284 (Firewire) compatible parallel port 305. ASIC printer controller 301 directs networking by the system via the Ethernet 306 from a local area network 307 and provides a mass storage interface via an ATA-4 compatible disc interface 308 to disc drive 309.
System data movement among main processor 300, system ASIC print controller 301, DRAM memory 310 and FLASH or ROM memory 311 are all accomplished via processor bus 302. System ASIC print controller 301 provides interface to printer engine via engine control signals 312 and video data output 313.
FIG. 4 illustrates the memory bandwidth requirement for the processor-initiated video output in the conventional system of FIG. 3. The processor-initiated video output is the most bandwidth intensive operation and must occur in real time. Three operations require processor bus 302 bandwidth: processor band clearing and write 406 of rasterized data to the output band buffer; the real-time read 407 of data from the printer engine; and real-time write 408 of data to the printer engine. This video output requires a total of 256 Mbytes/page for processor band clearing and write 406, 128 Mbytes/page for real-time read 407 and 128 Mbytes/page for real-time write 408 for a total of 512 Mbytes/page of processor bus 302 bandwidth. This translates into 136 Mbytes/sec for a 16 page/min printer.
FIG. 5 illustrates the data flow diagram for a conventional printer controller using a single processor bus. Three parts of the printer controller are identified with dashed-line boxes: DRAM 550, processor 551, and engine and peripheral interfaces 552. Operations and operation end points given in boxes in FIG. 5 require in many cases that the main processor yield the main processor bus to non-compute operations thereby slowing down overall processing speed. Each transfer of data is represented by a line and is labeled with the transfer size in Mbytes/page. Note that all transfer size requirements in FIG. 5 involve use of bus bandwidth on the common processor bus 302 in FIG. 3. Table 1 gives a complete list of the bus bandwidth requirements for each major controller operation. Specific operations in FIG. 5 may be cross-referenced to the list given following Table 1, which also shows the bus bandwidth requirements for each major controller operation.
These data paths are detailed below. Note: DMA is direct memory access; PCI
1. Networking: Processor Bus 120 Mbytes/page
From PDL input 500 to DMA 531 to PCI buffer 501 to DMA 521 to mbuffer 502 to DMA 522 to socket buffer 503.
2. Spooling: Processor Bus 80 Mbytes/page
From socket buffer 503 to DMA 523 to temporary buffer 504 to DMA 524 to DOS buffer 505 to DMA 532 to disc write DMA 506.
3. Stream I/F: Processor Bus 80 Mbytes/page
From disk read DMA 507 to DMA 533 to DOS buffer 508 to DMA 525 to stream buffer 510.
4. Image Filter: Processor Bus 80 Mbytes/page
From stream buffer 510 to DMA 526 to temporary buffer 511 to filter 512 to image buffer 513.
5. Color Conversion: Processor Bus 47 Mbytes/page
From image buffer 513 to color conversion 515 to converted image buffer 516.
6. Text Interpretation: Processor Bus 4 Mbytes/page
From font decompression 545 to font buffer 543.
7. Graphics Interpretation: Processor Bus 64 Mbytes/page
From display list generation 540 to display list buffer 544.
8. Band Clearing: Processor Bus 128 Mbytes/page
From band clearing operation 541 to output band buffer 530.
9. Rendering and Compression: Processor Bus 43 Mbytes/page
From render and compress operation 538 to compressed buffer 542.
10. Compressed Output Data: Processor Bus 11 Mbytes/page
From compressed buffer 542 to uncompress and screen operation 539.
11. Decompress and Screen: Processor Bus 139 Mbytes/page
From uncompress and screen operation 539 to output band buffer 530.
12. Video Output Data: Processor Bus 256 Mbytes/page
From output band buffer 530 to DMA 534 to video output 535.
This invention comprises a shared-memory printer controller architecture with a dedicated direct memory access (DMA) controller allowing engine data to be transferred while the processor maintains its ability to access instructions and data.
In earlier systems, during the real-time transfer of data from memory to the printer engine, the processor is unable to access the processor bus. By partitioning the memory into shared and local, it becomes possible to avoid such processor bottlenecks.